1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a charge storing means inside a gate insulating film between a channel forming region and a gate electrode of a memory transistor and having as its basic operation electrically injecting a charge (electrons or holes) into the related charge storing means to store or to extract the charge from the charge storing means and to a method of reading the same.
Specifically, the present invention relates to application of predetermined bias voltages to a source and drain or a gate of a selected memory transistor or non-selected memory transistor which has for example a plenarily dispersed charge storing means or for which a threshold voltage distribution is set narrow so as to supply an inhibit voltage for effectively preventing erroneous reading of the selected memory transistor and the non-selected memory transistor at the time of reading to the selected memory transistor and so as to control the threshold voltage in an erased state.
2. Description of the Related Art
In an advanced information society such as a high speed and wide area network society, there is a large need for large capacity file memories and large capacity AV use memories. At the present time, as large capacity memory systems for storing one gigabyte (GB) or more of data, disk memory systems using hard disks, optical disks, and other disks as the recording media have been used. There has been active research for replacing this big market with nonvolatile semiconductor memories in recent years.
However, while a nonvolatile semiconductor memory matches with the trend toward reduction of size and reduction of weight of hardware, the memory bit capacity is still insufficient at the present time and nonvolatile semiconductor memory (flash memory) having a large capacity of 1 gigabit (Gb) or more has yet been implemented. Further, in the above nonvolatile semiconductor memory, in addition to the insufficient storage capacity, the bit cost has not sufficiently been reduced in comparison with the disk memories. It is important to increase the bit capacity of the nonvolatile semiconductor memory for solving these problems.
There are generally the following two methods for increase the bit capacity of a nonvolatile semiconductor memory. The first method is to use a method of using a finer design rule in VLSI technology for miniaturization or scaling with the advanced circuit system of the memory cell and device structure so as to reduce a chip size occupied by the memory cell array and peripheral circuits. The second method is to use a method of making multilevel memory cells and making a single memory transistor store a plurality of bits to raise the storage capacity with the same bit capacity.
In the former method, miniaturization is carried out by the so-called scaling rule, but various inherent problems exist concerning the scaling in order to realize a large capacity nonvolatile semiconductor memory of 1 Gb or more by a plenarily contiguous floating gate (FG) type flash memory. In particular, the problems that reduction of an operating voltage becomes difficult due to the fact that the thickness of the tunnel oxide film is not scaled have been pointed out (refer to Nikkei Microdevices, January and February 1997).
Namely, in an FG type flash memory, the charges in the floating gate are held mainly by the thickness of the tunnel oxide film. Therefore, according to theoretical analysis of a back tunneling current from the floating gate, the thickness of the tunnel oxide film is physically limited to about 6 nm. However, at present, before this physical limit, there have been severe limit of thickness of tunnel oxide film due to the stress induced leakage current (SILC) in FG type flash memory. In the current FG type, it is pointed out, a high electric field of about 10 to 12 MV/cm is used for writing of data. Therefore stress induced leakage current (SILC) of the tunnel oxide film is increased along with the increase after the endurance W/E cycles number of times, and this determines the effective limit of thickness of the tunnel oxide film. Due to the limitation on the film thickness due to the increase of the stress induced leakage current, it is difficult to reduce the thickness of the tunnel oxide film to as low as the a theoretical limit of 6 nm. The practical limit of the thickness of the tunnel oxide film has therefore been considered to be 8 nm. For low voltage writing operation, the tunnel oxide film must be made thin, but the limit of reduction of thickness of the tunnel oxide film contradicts with the scaling rule for lowering the operating voltage and therefore the scaling of the operating voltage has become difficult. As a result, the reduction of the area of the peripheral circuits etc. has become very difficult.
On the other hand, in a metal (generally conductive gate) -nitride-oxide semiconductor (MNOS) type nonvolatile semiconductor memory, carrier traps in a nitride film SixNy (0&lt;x&lt;1, 0&lt;y&lt;1) mainly responsible for holding the charges or at an interface between a top oxide film and the nitride film spreads dispersedly in the direction of film thickness or the planar direction, so the data retention characteristic depends upon an energy-like and spatial distribution of the charge captured by the carrier traps in the SixNy film in addition to the thickness of the tunnel oxide film. Where a leakage current path is locally generated in this tunnel oxide film, in the FG type, lots of charges leak by passing through the leakage path, while in the MONOS type, the local charges in the vicinity of the leakage path merely locally leak by passing through the leakage path.
For this reason, the problem of the reduction of thickness of the tunnel oxide film in MONOS is not as serious as in the FG type, and a scaling property of the tunnel oxide film in a miniaturized MONOS type memory transistor having an extremely short gate length is better than that of the FG type.
In order to implement a large scale nonvolatile semiconductor memory by reducing the cost per bit and increasing the bit capacity of such a MONOS type or MNOS type nonvolatile memory, it is essential to utilize a single-transistor type memory cell structure.
In a conventional MONOS type nonvolatile memory, however, the mainstream is the two-transistor type in which a selection transistor is connected to the memory transistor. Establishment of a memory cell technology for utilizing a single-transistor memory cell has been long been a goal. For establishment of this single-transistor memory cell technology, it is important not only to optimize the device structure, mainly the gate insulating film containing the charge storing means, and improve the reliability, but also to improve the disturb characteristic.
For a MONOS type single transistor memory cell, a technique for avoiding a read disturb is described in for example Japanese National Patent Publication (Tokuhyo) No. 8-507411.
According to the details described in this publication, a read disturb is caused due to the weak write field applied to an ONO film. Therefore the source of the selected memory transistor is biased up to the gate read voltage to set the same voltage between the source and the gate and thereby avoid a read disturb. Further, the threshold voltage at the time of erase operation is set to a negative value. In this case, the thickness of the tunnel insulating film is set to 1.6 nm as typical value.
However, in the technique described in the above publication, the following problems exist.
(1) Since the thickness of the tunnel insulating film is typically relatively thin (1.6 nm), the amount of shift of the threshold voltage in a depletion direction due to the injection of holes at the time of erase operation becomes large. For this reason, at the endurance operation, traps are formed in the tunnel insulating film due to the injection and extraction of the holes and, as a result, the endurance characteristic is deteriorated.
(2) It is difficult to scale the drain read voltage (applied voltage V.sub.cc) corresponding to the scaling of the memory cell.
For example, in order to increase the threshold voltage -2V in the erased state to about 0.5V after source bias, a bias voltage Vr of the source and gate of about 2V becomes necessary. Accordingly, the drain read voltage supplied to the drain in this case must be about 3V at the lowest. Scaling of this drain read voltage is difficult since even if the memory transistor is miniaturized, the source bias voltage Vr does not change much at all. In actuality, in the above publication, the typical value of the drain read voltage (power supply voltage V.sub.cc) is described as 3V to 6V.
(3) In the publication, writing of a non-selected transistor connected to the selected word line can be inhibited by setting the source and drain at the supply voltage V.sub.cc. For this reason, in a shorter gate length region (particularly in the case of a gate length of 0.2 .mu.m or less), erroneous writing or erroneous erasing of memory cell in a non-selected column connected to a non-selected word line cannot be inhibited unless the non-selected word line is set to a positive voltage of a certain high extent. However, among memory cells connected to a non-selected word line, in a memory cell to which a source line and a bit line of the selected memory cell are commonly connected (memory cell of non-selected row in selected column), the voltage of the source and drain is determined according to the write condition of the selected memory cell, so cannot be freely raised. As a result, this memory cell of the non-selected row in the selected column exhibits a weak written bias stress and, in addition, the thickness of the tunnel insulating film is a relatively thin 1.6 nm as a typical value, therefore a write disturb cannot be avoided.
In order to realize a MONOS type single-transistor memory cell, irrespective of the fact that a desired disturb characteristic must be guaranteed after a large number of endurance cycles, the publication has no description on the disturb characteristic after the endurance cycles.
Therefore, the present inventors performed various studies for investigating the factors determining the read disturb margin of a nonvolatile semiconductor memory device in which the charge storage layer is planarly dispersed, as represented by the MONOS type, and performed the endurance of the MONOS memory transistor by using an NOR type memory cell a large number of times to determine the problems relating to the deterioration of the read disturb characteristic.
As a result, it became clear that there are two problems in the read gate voltage dependency of the read disturb characteristic after 10.sup.6 endurance cycles. Note that, the voltage supplied to the selected word line and selected bit line at this time was 1.5V, and the voltage of a non-selected word line, non-selected bit line, and all source lines was set to be 0V.
As a first problem, it was verified that the selected memory transistor or non-selected memory transistors of the same row with gates connected to the selected word line to which a voltage (1.5V) is supplied is indispensable to be written weakly as the reading time increases. As a result, the gate threshold voltage in the erased state increased along with the elapse of time and the difference of the gate threshold voltage (V.sub.th window width) between the written state and erased state after 10 years did not become sufficient.
Further, as a second problem, it was verified that, by lowering the V.sub.th in the erased state by a deep erase operation to the depletion direction by for example the injection of holes and increasing the V.sub.th window width of the memory transistor at the time of erasing and by a roll-off of the gate threshold voltage due to a short channel effect, the V.sub.th window shifts relatively to a negative side of the threshold voltage when the gate length becomes shorter, and the gate threshold voltage in the written state became smaller than the voltage of the selected word line (read gate voltage) when the reading is carried out for 10 years. As a result, when reading the data in the written state, a current flows between the bit line and the source line similar to the time of reading the erased state, therefore single-transistor memory cell operation becomes difficult. Further, where the gate threshold voltage in the erased state of the non-selected transistor is too low, the transistor becomes depleted, the problem of a flow of leakage current at the time of reading occurs even if the gate voltage is 0V, and single-transistor memory cell operation becomes difficult.
These phenomena are thought to be inherent even in the usual FG type, but in the FG type, the thickness of the tunnel oxide film is 8 nm or more. Therefore even when the selected word line voltage at the time of reading is a high 3.3V, there is no problem of "soft write". Further, in the FG type, the gate threshold voltage V.sub.th in the erased state can be set high in comparison with the MONOS type. The two above describing problems are problems manifested in the case of a single-transistor memory cell in which the gate length is miniaturized in a memory element of MONOS type or the like in which the reduction of thickness of the tunnel insulating film is possible in comparison with the FG type and the charge storing means is made planarly dispersed.